FIG. 1A shows a cross-section of a conventional integrated device 100, e.g., a conventional OR gate, formed by multiple transistors. As shown in FIG. 1A, the integrated device 100 includes an n+ substrate 116, an n− epitaxial layer 118 grown on the substrate 116, and transistors 102 and 122 formed based on the epitaxial layer 118. The substrate 116 and the epitaxial layer 118 form a drain region shared by the transistors 102 and 122. The transistor 102 includes a p-well 110 and a p-type guard ring 112 formed in the epitaxial layer 118, and the guard ring 112 surrounds the p-well 110. The transistor 102 also includes an n+ well 108 formed in the p-well 110, and a source electrode 106 formed atop the n+ well 108. The transistor 102 also includes an insulating layer 114 formed atop the guard ring 112, and a gate electrode 104 formed atop the insulating layer 114. The gate electrode 104, the insulating layer 114, and the guard ring 112 form a capacitor ring surrounding the p-well 110. The capacitor ring can terminate an electric field extending from the p-well 110 to the guard ring 112 such that the drain-source breakdown voltage and the un-clamp inductive switching (UIS) current, e.g., the avalanche current, of the transistor 102 are relatively high. Similar to the transistor 102, the transistor 122 includes a p-well 130, an n+ well 128, a source electrode 126, a p-type guard ring 132, an insulating layer 114, and a gate electrode 124. The gate electrode 124, the insulating layer 114, and the guard ring 132 form a capacitor ring surrounding the p-well 130. The capacitor ring can terminate an electric field extending from the p-well 130 to the guard ring 132 such that the drain-source breakdown voltage and the UIS/avalanche current of the transistor 122 are relatively high. As shown in FIG. 1A, the source electrodes 106 and 126 are connected such that the transistors 102 and 122 share a source terminal labeled “S.” The transistors 102 and 122 also share a drain terminal labeled “D.” Thus, the transistors 102 and 122 form an OR gate.
FIG. 1B shows a top view of the integrated device 100 in FIG. 1A. For clarity, some portions of the integrated device 100 are not shown in FIG. 1B. More specifically, FIG. 1B shows a top view of the p-well 110 and the guard ring 112 of the transistor 102, and the rest of the transistor 102 is not shown. FIG. 1B also shows a top view of the gate electrode 124 and the source electrode 126 of the transistor 122, and the rest of the transistor 122 is covered by the electrodes 124 and 126. In the example of FIG. 1B, the p-well 110 and the guard ring 112 have planar shapes similar to a square. The p-well 110 has a side length DW, the guard ring 112 has a uniform width DR, and the gap between the p-well 110 and the guard ring 112 has a uniform width DG. Thus, a side length DTR of the guard ring 112 is given by:DTR=DW+2*DR+2*DG.
Thus, the transistor 102 occupies at least a planar area of D2TR, i.e., (DW+2*DR+2*DG)2. Because the transistors 102 and 122 have similar sizes, the transistors 102 and 122 together occupy at least a planar area of 2*D2TR. Additionally, there is a gap 120 between the transistors 102 and 122 to separate the gate electrodes 104 and 124. Hence, the integrated device 100 occupies at least A planar area of 2*D2TR plus the planar area of the gap 120. The size of the integrated device 100 may be relatively large because of the guard rings 104 and 124 and the gap 120.